In this concern I would like to know your opinion about the "new" eSIM technique.
- Technically -> complexity and space requirements (as space was your argument for the dual-sim implementation)?
- You like it or rather stick to the conventional µSIM (reasons?)
Well, that might be a dealbreaker for people because 3G is going to get phased out before 2G. Providers want all the frequencies and bandwidth for 4G/5G.
And no, 3G doesn’t consume less power. The overhead of the protocol is AFAIK 15% like ATM. It isn’t even native TCP/IP. EDIT: 4G/5G has way better latency due to that.
After posting I could read that he might have found a better alternative. We’ll see.
If so that would even make things worse because there are countries/providers already not even having 2G active anymore.
So unlucky owners of the mainboard not having 2G and even 3G some day would hold a new unit degraded to crap without any reception option.
That would be the biggest frustration someone could experience.
So let’s hope the latest finding of @Leo_TheCrafter gives a working solution.
This could be an optio if eSIM becomes more popular and wouldn’t be hard to implement, but for now I’ll stick with my standard SIM solution. A eSIM would be a great option to make space for more funktionality in the future. Thanks for the post.
I’m very far right now and I hope I can finfish most of it this year. I’m drawing some scematics and refining the board layout right now.
Reading this some more came to my mind that was discussed here in the past.
There were more features requested which FP2 atm. does not deliver.
How does it look for your motherboard with these features, are they possible, maybe later by utilization with module upgrades?
VoLTE is possible and even high standard bluetooth support is available
I’m currently drawing scematics for CPU power supply, but because this is all subject to change, I can’t release renders just jet, beacuse there will be a lot of changes in this section of the board.
I have now redesigned the PMIC for the CPU. It now has two voltages (CORE VCC0, CORE VCC1) for longer battary life.
I like your subtle progress in the background popping up once in a while with results and not only bla - bla bla. That’s not very common these days.
Many thanks for keeping us updated.
Thanks for that feedback. I can post more renders when I’m certain that the renders won’t change too much.
I added an underfill-like glue around the antana connetctors to prevent damage when removing the connectors. It has a rubber like consistency and is easy to remove when the device has to be serviced (component level), but prevents damage to the anatana tuning components, a damage that’s hard and expensive to repair.
I am able to implement a dual BIOS system by using a special controller and two WLCSP 128Mbit SPI flash ICs. This can simplify flasing a new BIOS, but also make it less likely to brick the device
Do you really need a BIOS? Most ARM chips don’t need one, but I can understand it makes OS development easier.
On Android, you have the Recovery ROM that you can use to prevent bricking (to some extent). From what I understand, it’s just booting to a different address than the System ROM.
It’s important that you have a BIOS when you want the device to be able to run linux. It also makes it easier to diagnose faults. E.g. the SMC could have a programm running that checks RAM and other important informations and reports if there is something wrong with the system over the JTAG connector. The SMC doesn’t have that much storage, but it needs to be able to check a lot of power rails and needs to be able to set the PWROK signals before the CPU even starts. And when developing a BIOS it could happen that you accedently brick the device when you only have one BIOS.
I run Linux on FPGA chips without BIOS (Xilinx Zynq), but it’s true it’s a lot of pain less if “something” can check power, memory, and other hardware stuff.
I remember “bricking” a motherboard flashing a wrong BIOS version so I’ll definitely won’t argue about a second chip
And I trust your judgment if you think it can be laid out without requiring too much additional power, or €
The NOR flash ICs cost only around 5€ and the are from good quality, made by winbond and they also consume just 1mA and that’s under full operation. The SMC can even write/read them at the same time
I can now post renders that will look almost final, beacuse now all the important components are placed. There will still be changes, but only some filter capacitors here and there some temperature sensors. If you have any questions, I can answer them for you.
Here is a view of the board without soldermask so that it appears semi-transparent. Be aware that this is for show-purpose only, beacuse such a transparent board is impossible to manufacture. But it shows all the traces in the PCB.
And in this render I removed one RAM chip and the CPU to expose the traces for the RAM signals
I now start to get to the point where I’m almost finished and maybe some of you know somebody that can look over it. I think there are quite some things I did wrong, so my next stept would be to let sb have a look at the whole board. If somebody likes to look over it, I can send him the files, I did everything in KiCat, but KiCat if free and opensource and even available on Windows and Linux.